PCB SIGNAL INTEGRITY TOOL

PCB Impedance Calculator

Estimate single-ended or differential PCB trace impedance, solve trace width for a target value, and compare propagation delay using your actual dielectric constant, copper thickness, reference-plane spacing, and pair gap.

Microstrip and stripline Single-ended and differential mm and mil dimensions
Calculate Impedance Review Validation Practice
CONTROLLED IMPEDANCE STACKUP VIEW
TARGET 50 Ω
MODEL MICROSTRIP
ESTIMATED Z 55.6 Ω
ACTIVE MODEL Hammerstad–Jensen quasi-static microstrip

INTERACTIVE STACKUP ESTIMATE

Calculate Impedance or Solve Trace Width

Select the transmission-line geometry, enter finished dimensions, and use the laminate Dk at the intended operating frequency. Results are first-pass values for stackup planning and fabrication discussion.

STACKUP INPUTS

Geometry and Material

Transmission-Line Geometry
Calculation Mode
Dimension Units
Use laminate Dk at the relevant frequency.
mm
Finished dielectric thickness beneath the trace.
mm
Use the finished etched conductor width.
mm
Include plating when applicable.
Ω
Used for target comparison or width synthesis.

ACTIVE CROSS-SECTION

Surface Microstrip

H–J MODEL
REFERENCE PLANE
W S T
H
REFERENCE PLANE
W
0.300 mm
H
0.200 mm
T
0.035 mm
Quasi-static microstrip estimate

Includes finite copper thickness in the Hammerstad–Jensen single-line model. Solder mask, roughness, etch shape, and frequency dispersion are not modeled.

Geometry within the recommended screening range
ESTIMATED CHARACTERISTIC IMPEDANCE 55.64 Ω Single-ended surface microstrip
TARGET COMPARISON +5.64 Ω

Increase trace width to lower impedance toward the 50 Ω target.

Finished Trace Width 0.300 mm
Single-Line Z₀ 55.64 Ω
Effective Dielectric Constant 3.005
Propagation Delay 5.78 ps/mm 146.9 ps/in
Propagation Velocity 57.7% c
±10% Width Sensitivity 52.7–59.0 Ω
MODEL TYPE Hammerstad–Jensen

CALCULATION BASIS

Models Used by the Calculator

The page uses closed-form transmission-line estimates for fast stackup screening. The same model is used in forward calculation and trace-width synthesis, so the displayed target result remains internally consistent.

01

Surface Microstrip

Z₀ = Zair(W/H,T/H) ÷ √εeff

Hammerstad–Jensen quasi-static equations estimate effective permittivity and include a finite conductor-thickness width correction.

02

Symmetric Stripline

Z₀ ≈ 60/√Dk · ln[4B ÷ 0.67π(0.8W+T)]

The closed-form IPC-style stripline expression uses total reference-plane spacing B and finished conductor dimensions.

03

Differential Pair

Zdiff = 2Z₀ · coupling factor(S/H)

Edge-coupled pair impedance is estimated from the single-line result and normalized edge-to-edge spacing. Final coupled structures require field-solver verification.

04

Trace-Width Synthesis

Find W where |Z(W) − Ztarget| → 0

A bounded binary search solves trace width using the active geometry, dimensions, Dk, thickness, and pair spacing.

INPUT QUALITY

Use Finished Stackup Values, Not Nominal Artwork Values

Impedance accuracy depends more on the quality of the stackup inputs than on extra decimal places in the result.

Dielectric Height

Use pressed dielectric thickness from the fabricator stackup. For symmetric stripline, enter the finished plane-to-plane spacing.

Finished Copper Geometry

Use etched width and final copper thickness. Plating, trapezoidal sidewalls, and local process compensation can shift production impedance.

Frequency-Appropriate Dk

Datasheet Dk varies with test method, resin content, glass weave, and frequency. Use the fabricator’s modeling value when available.

Differential Pair Gap

Enter copper edge-to-edge spacing, not center-to-center pitch. Nearby copper pours and asymmetrical reference conditions are outside this model.

ENGINEERING BOUNDARY

What This Calculator Includes—and What Fabrication Must Verify

Included in the Estimate

  • Surface microstrip and symmetric stripline
  • Single-ended and edge-coupled differential estimates
  • Finite copper thickness in the single microstrip model
  • Target comparison and inverse trace-width solution
  • Effective Dk, velocity, and propagation delay

Verify Outside the Calculator

  • Solder mask, copper roughness, and frequency dispersion
  • Etch trapezoid, plating distribution, and process tolerances
  • Asymmetric stripline, coplanar ground, and nearby copper
  • Glass-weave effects, losses, vias, pads, and connectors
  • Fabricator field-solver model and TDR coupon results

CONTROLLED IMPEDANCE IS A MANUFACTURING PROCESS

Use this result to start the stackup discussion—not to replace fabricator modeling and TDR verification.

Review Engineering Validation Open Technical Whitepapers View Reference Platforms

NEXT ENGINEERING CHECKS

Related PCB and System Calculators

Continue from geometry and impedance into current capacity, voltage loss, copper specification, and system-level design checks.

01

PCB Trace Width Calculator

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Calculate trace width 02

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Check trace resistance, voltage drop, and conductor loss across a defined route length.

Check voltage drop 03

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Convert copper weight into nominal thickness in micrometers, millimeters, and mils.

Convert copper weight 04

PCB Via Current Calculator

Estimate via resistance, current density, voltage drop, and parallel-via requirements.

Calculate via current 05

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Screen board outline, keepouts, connector projection, and enclosure clearance.

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Estimate platform power demand across CPU, memory, storage, expansion, and peripherals.

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PCB IMPEDANCE FAQ

Practical Questions Before You Release the Stackup

Use the calculator for early geometry screening, then confirm the production model with your PCB fabricator.

These answers focus on microstrip, stripline, differential pair spacing, Dk selection, and controlled-impedance verification.

Discuss a Controlled-Impedance Stackup
How do I calculate 50 ohm PCB microstrip impedance?

Enter finished trace width, copper thickness, dielectric height, and frequency-appropriate Dk. Use Solve Width to estimate the conductor width needed for a 50 Ω target.

What dimensions are required for a PCB stripline impedance calculation?

Use total reference-plane spacing, finished trace width, finished copper thickness, and laminate Dk. This page assumes the trace is centered between symmetric planes.

How is differential PCB impedance calculated from pair spacing?

The calculator adjusts the single-line impedance using normalized edge-to-edge gap. Smaller spacing increases coupling and usually lowers differential impedance.

Should I enter nominal or finished PCB trace width?

Use finished etched width whenever possible. Artwork width can differ after etching, plating, and process compensation, especially on outer layers.

Which dielectric constant should I use for controlled impedance?

Use the fabricator’s modeling Dk or laminate Dk measured near the operating frequency. Datasheet nominal values may use a different test method.

Can this PCB impedance calculator replace a field solver or TDR coupon?

No. It provides a first-pass geometry estimate. Final controlled impedance requires the fabricator’s stackup model, process compensation, and production coupon verification.